JRC’s Custom Design for Defense Operations closes this gap. We deliver radiation-hardened semiconductor solutions that are custom-engineered for reliability, power efficiency, and long-term durability in the most unforgiving operational environments. In the face of evolving nuclear modernization efforts and next-gen deterrence platforms, traditional semiconductors fall short. Radiation, extreme conditions, and interoperability challenges can compromise mission success.
JRC provides end-to-end design of radiation-hardened microelectronics, using our proprietary LEAP (Layout Design through Error Aware Positioning) methodology to ensure ultra-low Soft Error Rate (SER) and robust latch-up immunity. Using our proprietary LEAP methodology, we optimize circuit design to mitigate Soft Error Rate (SER) and latch-up sensitivity, ensuring unmatched performance and resilience in the most challenging operational environments
Core assets supporting this capability
Proprietary cell designs optimized for latch-up resistance and layout-based SER mitigation
Internal tools for radiation analysis & design software, simulating, validating, and hardening circuits
Defense-cleared engineers with deep expertise in radiation-hardened ASIC development
Secure facilities enabling rapid iteration and reliability qualification
