Radiation-Hardened
Semiconductor
Technology

Engineering Resilient Microelectronics for the Future of National Defense

Introduction
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JRC is recognized as a world leader in radiation-hardened semiconductor technology, combining decades of engineering excellence with advanced microelectronics innovation integral to strengthening national security and strategic defense programs. We help deliver reliable, mission-critical microelectronics with unmatched performance and durability for the most demanding aerospace defense environments.

The future of national defense depends on resilient systems that can endure the harshest conditions and deliver without fail. As modern strategic deterrent systems and aerospace missions become more complex, the microelectronics at their core must be mission-ready, radiation-hardened, and built for operational continuity. At JRC, we deliver microelectronics that meet this challenge head-on, supporting strategic deterrence and national defense missions with unmatched reliability.

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We specialize in
JRC
What We Provide

JRC engineers develop and deliver custom radiation-hardened semiconductor technology for mission-critical aerospace and defense applications.

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Standard Cell Libraries (LEAP™)
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ASIC design for mission critical conditions.
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Radiation analysis and design tools
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Custom microelectronic design for mission-critical defense systems
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End-to-end verification and qualification
Proprietary Technology
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Our proprietary technology is engineered for extreme aerospace and defense environments, giving mission partners the confidence to deliver trusted, fabrication-ready designs. Chips generated using our IP and services validated to withstand radiation effects like Total Ionizing Dose (TID), Single Event Effects (SEE), and latch-up, ensuring mission continuity when failure is not an option.
Accelerating Radiation-Hardened Chip Development with JRC’s LEAP Standard Cell Library

Radiation effects like single-event upsets and latch-ups have long forced designers to rely on Triple Mode Redundancy (TMR), a method that triples circuit size, power use, and cost while still leaving blind spots in protection. When NASA’s High Performance Space Computer (HPSC) hit delays and mounting program risk with TMR, JRC’s LEAP Standard Cell Library changed the equation. By embedding radiation hardening directly into the cell itself, LEAP delivered 10× greater resilience with only a fraction of the size, power, and performance penalties, accelerating development, reducing cost, and enabling next-generation space processors once thought impossible.

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Our Specialized Tools

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Our Specialized Tools

Radiation-hardened, customizable, and mission tested

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Accuro Tools Suite

High-speed physics based software for radiation modeling.

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Custom IC Design

Tailored for space-grade operations

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On-Site Radiation Testing Support

We partner directly with government test facilities and labs to simulate mission conditions

005 SPECIALIZED TOOLS
JRC
What Sets Us Apart
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    Complete 12nm standard cell library: 13K+ rad-hard cells for full digital logic coverage
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    Rad-hard enablement baked in to the logic cell to reduce program risk
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    Our logic cells allow your circuit designers to focus on the overall chip design instead of radiation mitigation designs that introduce program risk
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    Accuro Tool Suite – Physics based, high-speed modeling reduces design risk and time-to-tapeout
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    Custom Support Teams – We don’t just license IP, we engineer alongside you, providing full-cycle design, simulation, and radiation tested
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    TCAD + EDA expertise that flattens the learning curve
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    Accurate prediction of error rates for custom IP blocks
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    Specialized flip-flop & SRAM cell design experience for space-grade builds trusted performance, used across NASA and spaceflight-critical program
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    LEAP standard cells eliminate the need for Triple Mode Redundancy (TMR), delivering radiation-hard protection in a single cell rather than triplicates, saving significant power, performance, and area (PPA)
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    Minimized design penalties unlike TMR, LEAP reduces overhead in power consumption and circuit area, enabling more efficient, compact, and reliable rad-hard designs
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    Superior resilience at advanced nodes as processes shrink (Intel 18a, TSMC 2N, GAA, etc.), voting cells in TMR become too close and risk simultaneous failure. LEAP avoids this, providing reliable protection where TMR falters
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    10^5× harder than commercial IP LEAP standard cells deliver unmatched hardness compared to commercial alternatives or legacy RHBD techniques
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    Simplified design cycle circuit designers can focus on higher-level logic and system performance instead of managing TMR triplication and voting logic
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    Better than alternative RHBD techniques (like DICE) while DICE offers some radiation tolerance, it cannot match the hardness, efficiency, or scalability of LEAP
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    Trusted by the Missile Defense Agency, NASA, and the United States Navy
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    Custom-built, tailored for modern foundries and defense integration
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Why JRC

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